# Enable internal termination resistor on LVDS 125MHz ref_clk
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_p]
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_n]

# Define I/O standards
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_3_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_3_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_2]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_0]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_1]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_3]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_0_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_0_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_1_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_1_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_2_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_2_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_txc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_txc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_txc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_txc]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_clk_n]
set_property IOSTANDARD LVCMOS25 [get_ports {ref_clk_oe[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ref_clk_fsel[0]}]
set_property PACKAGE_PIN L21 [get_ports {rgmii_port_1_rd[0]}]
set_property PACKAGE_PIN L22 [get_ports mdio_io_port_0_mdio_io]
set_property PACKAGE_PIN T19 [get_ports {rgmii_port_1_rd[2]}]
set_property PACKAGE_PIN K20 [get_ports mdio_io_port_1_mdio_io]
set_property PACKAGE_PIN D20 [get_ports rgmii_port_3_rxc]
set_property PACKAGE_PIN C20 [get_ports rgmii_port_3_rx_ctl]
set_property PACKAGE_PIN E21 [get_ports {rgmii_port_3_rd[1]}]
set_property PACKAGE_PIN D21 [get_ports {rgmii_port_3_rd[3]}]
set_property PACKAGE_PIN N19 [get_ports rgmii_port_1_rxc]
set_property PACKAGE_PIN N20 [get_ports rgmii_port_1_rx_ctl]
set_property PACKAGE_PIN J18 [get_ports mdio_io_port_0_mdc]
set_property PACKAGE_PIN K18 [get_ports reset_port_0]
set_property PACKAGE_PIN R20 [get_ports {rgmii_port_1_rd[1]}]
set_property PACKAGE_PIN R21 [get_ports {rgmii_port_1_rd[3]}]
set_property PACKAGE_PIN M17 [get_ports mdio_io_port_1_mdc]
set_property PACKAGE_PIN B19 [get_ports rgmii_port_2_rxc]
set_property PACKAGE_PIN E15 [get_ports {rgmii_port_2_rd[2]}]
set_property PACKAGE_PIN D15 [get_ports {rgmii_port_2_rd[3]}]
set_property PACKAGE_PIN F18 [get_ports {rgmii_port_3_rd[0]}]
set_property PACKAGE_PIN E18 [get_ports {rgmii_port_3_rd[2]}]
set_property PACKAGE_PIN M19 [get_ports rgmii_port_0_rxc]
set_property PACKAGE_PIN M20 [get_ports rgmii_port_0_rx_ctl]
set_property PACKAGE_PIN N22 [get_ports {rgmii_port_0_rd[2]}]
set_property PACKAGE_PIN P22 [get_ports {rgmii_port_0_rd[3]}]
set_property PACKAGE_PIN J21 [get_ports {rgmii_port_0_td[1]}]
set_property PACKAGE_PIN J22 [get_ports {rgmii_port_0_td[2]}]
set_property PACKAGE_PIN P21 [get_ports {rgmii_port_1_td[0]}]
set_property PACKAGE_PIN J20 [get_ports {rgmii_port_1_td[2]}]
set_property PACKAGE_PIN K21 [get_ports {rgmii_port_1_td[3]}]
set_property PACKAGE_PIN G20 [get_ports rgmii_port_2_rx_ctl]
set_property PACKAGE_PIN G21 [get_ports {rgmii_port_2_rd[0]}]
set_property PACKAGE_PIN G19 [get_ports {rgmii_port_2_td[1]}]
set_property PACKAGE_PIN F19 [get_ports {rgmii_port_2_td[2]}]
set_property PACKAGE_PIN D22 [get_ports rgmii_port_2_tx_ctl]
set_property PACKAGE_PIN C22 [get_ports mdio_io_port_2_mdio_io]
set_property PACKAGE_PIN C18 [get_ports {rgmii_port_3_td[0]}]
set_property PACKAGE_PIN B16 [get_ports {rgmii_port_3_td[2]}]
set_property PACKAGE_PIN B17 [get_ports {rgmii_port_3_td[3]}]
set_property PACKAGE_PIN P17 [get_ports {rgmii_port_0_rd[0]}]
set_property PACKAGE_PIN P18 [get_ports {rgmii_port_0_rd[1]}]
set_property PACKAGE_PIN M21 [get_ports {rgmii_port_0_td[0]}]
set_property PACKAGE_PIN M22 [get_ports rgmii_port_0_txc]
set_property PACKAGE_PIN T16 [get_ports {rgmii_port_0_td[3]}]
set_property PACKAGE_PIN T17 [get_ports rgmii_port_0_tx_ctl]
set_property PACKAGE_PIN N17 [get_ports {rgmii_port_1_td[1]}]
set_property PACKAGE_PIN N18 [get_ports rgmii_port_1_txc]
set_property PACKAGE_PIN J16 [get_ports rgmii_port_1_tx_ctl]
set_property PACKAGE_PIN J17 [get_ports reset_port_1]
set_property PACKAGE_PIN G15 [get_ports {rgmii_port_2_rd[1]}]
set_property PACKAGE_PIN G16 [get_ports {rgmii_port_2_td[0]}]
set_property PACKAGE_PIN E19 [get_ports rgmii_port_2_txc]
set_property PACKAGE_PIN E20 [get_ports {rgmii_port_2_td[3]}]
set_property PACKAGE_PIN A18 [get_ports mdio_io_port_2_mdc]
set_property PACKAGE_PIN A19 [get_ports reset_port_2]
set_property PACKAGE_PIN A16 [get_ports {rgmii_port_3_td[1]}]
set_property PACKAGE_PIN A17 [get_ports rgmii_port_3_txc]
set_property PACKAGE_PIN C15 [get_ports rgmii_port_3_tx_ctl]
set_property PACKAGE_PIN B15 [get_ports mdio_io_port_3_mdc]
set_property PACKAGE_PIN A21 [get_ports mdio_io_port_3_mdio_io]
set_property PACKAGE_PIN L19 [get_ports ref_clk_clk_n]
set_property PACKAGE_PIN L17 [get_ports {ref_clk_oe[0]}]
set_property PACKAGE_PIN K19 [get_ports {ref_clk_fsel[0]}]
set_property PACKAGE_PIN A22 [get_ports reset_port_3]

create_clock -period 8.000 -name rgmii_port_3_rx_clk -waveform {0.000 4.000} [get_ports rgmii_port_3_rxc]

create_clock -period 8.000 -name ref_clk_clk_p -waveform {0.000 4.000} [get_ports ref_clk_clk_p]

# IODELAY group for GMII-to-RGMII block
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells *_i/gmii_to_rgmii_0/U0/i_*_gmii_to_rgmii_0_0_idelayctrl]
set gmii_to_rgmii_0_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/gmii_to_rgmii_0/*delay_rgmii_rx*" } ] 
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 $gmii_to_rgmii_0_iodelay
set_property IDELAY_VALUE 13 $gmii_to_rgmii_0_iodelay

# IODELAY groups for the AXI Ethernet ports
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells *_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells {*_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]

#False path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }]
set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/SYNC_*/data_sync* }] -filter { name =~ *D }]
set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
#False path constraints from Control Register outputs
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/DUPLEX_MODE_REG*/C }]
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/SPEED_SELECTION_REG*/C }]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE0}]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S0}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE1}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S1}]

# For timing closure with the proper set_input_delay constraints

set port_0_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/axi_ethernet_0/*delay_rgmii_rx*" } ]
set_property IDELAY_VALUE 13 $port_0_iodelay
set port_1_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/axi_ethernet_1/*delay_rgmii_rx*" } ] 
set_property IDELAY_VALUE 12 $port_1_iodelay
set port_2_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/axi_ethernet_2/*delay_rgmii_rx*" } ] 
set_property IDELAY_VALUE 12 $port_2_iodelay

